1. Technical Field
The present invention relates to a test apparatus and a test method. Particularly, the present invention relates to a test apparatus and a test method, for testing memory under test which stores a data string including an additional error correction code. The present application claims priority from a Japanese Patent Application No. 2004-300782 filed on Oct. 14, 2004, the contents of which are incorporated herein by reference.
2. Related Art
With conventional semiconductor memory test apparatuses, the output from memory under test is logically compared with an anticipated value for each test cycle. With such an arrangement, in a case that the output matches the anticipated value in the comparison step, a “pass” determination is made, which means that the memory is acceptable. On the other hand, in a case that the output does not match the anticipated value, a “fail” determination is made, which means that the memory is unacceptable. Let us consider a case of testing memory under test such as flash memory, which operates in a manner in which the stored data is read out over multiple cycles in increments of pages, and error correction codes are added in increments of pages. In such a case, with conventional techniques, even if only one fall has been detected, determination is made that the memory under test is defective.
In some cases, the program disturb mode occurs in the flash memory. In this case, the data stored in any storage cell other than the writing target storage cell changes, leading to non-permanent software error. (see Non-Patent document 1) In practical use, in a case that such a software error has occurred, a memory controller for controlling the flash memory corrects the error in the data read out from the flash memory.    [Non-Patent document 1] A high density NAND Flash memory technology for a silicon movie era, FED Journal, Vol. 11, No. 3, 2000, pp. 76-78
With conventional semiconductor memory test apparatuses, in a case of detecting a fail in any test cycle, determination is made that the memory under test is defective. Let us consider a case of testing flash memory where it is in the nature of the flash memory under test to allow a certain amount of software error to occur. In such a case, the conventional semiconductor memory test apparatuses determine that such flash memory is defective.